DRAM cell arrangement and method for fabricating it
The invention relates to a DRAM cell arrangement and a method for fabricating it.
Endeavors are generally made to produce a DRAM cell arrangement with an ever higher packing density.
EP 0 852 396 describes a DRAM cell arrangement in which, in order to increase the packing density, a transistor of a memory cell is arranged above a storage capacitor of the memory cell. Active regions of the memory cells are in each case surrounded by an insulating structure arranged in a substrate. A depression is produced in the substrate for each memory cell, a storage node of the storage capacitor being arranged in the lower region of the said depression and a gate electrode of the transistor being arranged in the upper region of said depression. An upper source/drain region, a channel region and a lower source/drain region of the transistor are arranged one above the other in the substrate. The lower source/drain region is connected to the storage node at a first sidewall of the depression. The insulating structure adjoins a second sidewallxe2x80x94opposite to the first sidewallxe2x80x94of the depression, with the result that the storage node does not adjoin the substrate there. A capacitor electrode of the storage capacitor is formed by the addiffusion of dopant into the substrate. A lower region of the depression is widened by an isotropic etching process, areas of the upper region being protected in the process. As a result, a horizontal cross section of the lower region has a larger area than a horizontal cross section of the upper region. By virtue of the widening of the lower region of the depression, the surface area of a capacitor dielectric is enlarged and the capacitance of the storage capacitor is thus increased. A bit line adjoins the upper source/drain region and runs above the substrate. The depression is produced by etching the substrate selectively with respect to the bit lines with the aid of a strip-shaped mask whose strips run perpendicularly to the bit lines. A word line is produced together with a gate electrode by material being deposited in the upper region of the depression and being patterned. The gate electrode is insulated from the substrate and from the bit lines by a gate dielectric and by the insulating structure.
German patent specification 195 19 160 describes a DRAM cell arrangement in which a storage capacitor is arranged above a vertical transistor. With the aid of a mask widened by spacers, first trenches are produced, which cut through a layer sequence and are filled with a first insulation structure. Second trenches are then produced, which run transversely with respect to the first trenches and are shallower and wider than the first trenches. The second trenches are filled with a second insulation structure. The insulation structures are etched back to produce a lattice-shaped depression. After the production of the gate dielectric, in order to produce word lines, conductive material is deposited and etched back, with the result that, on account of the different widths of the trenches, the word lines are produced in a self-aligned manner in such a way that they run parallel to the second trenches. Parts of the layer sequence which are surrounded by the word lines act as the transistors. A capacitor dielectric is produced above the word lines and layer sequence, and a capacitor plate of the storage capacitors is produced above said capacitor dielectric. Upper parts of the layer sequence act as upper source/drain regions of the transistors and, at the same time, as capacitor electrodes of the storage capacitors. The memory cell can be fabricated with an area of 4F2, where F is the minimum feature size that can be fabricated in the technology used. Lower parts of the layer sequence act as bit lines which are isolated from one another by the first insulation structures and run parallel to the first trenches. Neither the word lines nor the bit lines have a high electrical conductivity.
The invention is based on the problem of specifying a DRAM cell arrangement whose word lines and bit lines can have a high electrical conductivity and which can, at the same time, be fabricated with a high packing density. Furthermore, the intention is to specify a method for fabricating it.
The problem is solved by means of a method for fabricating a DRAM cell arrangement, in which firstly first trenches running essentially parallel to one another are produced in a substrate. The first trenches are filled with isolating structures. By etching with the aid of a strip-shaped photoresist mask whose strips run transversely with respect to the first trenches, the substrate is etched selectively with respect to the isolating structures, with the result that depressions are produced. Areas of lower regions of the depressions are provided with a capacitor dielectric. A storage node of a storage capacitor is in each case produced in the lower regions of the depressions. Upper source/drain regions of the transistors are produced in such a way that they are in each case arranged between two mutually adjacent depressions of the depressions and between two mutually adjacent isolating structures of the isolating structures, and adjoin a main area of the substrate. At least first side walls of the depressions are provided with a gate dielectric in upper regions of the depressions. Lower source/drain regions of the transistors in the substrate are formed in such a way that they are electrically connected to the storage nodes, with the result that in each case one of the transistors and one of the storage capacitors are connected in series and form a memory cell. By depositing and patterning conductive material, word lines are produced, which run transversely with respect to the isolating structures and above the main area, and, adjoining them, gate electrodes of vertical transistors are produced, which are each arranged in one of the depressions and are electrically insulated from the storage nodes. An insulating layer is produced over the word lines. Insulating spacers are produced on side walls of the word lines by depositing material and etching it back. With the aid of a strip-shaped photoresist mask whose strips run essentially parallel to the isolating structures, etching is effected selectively with respect to the insulating layer and the spacers until the upper source/drain regions are uncovered. Bit lines are produced which make contact with the upper source/drain regions.
The problem is furthermore solved by means of a DRAM cell arrangement, in which a depression is provided in a substrate for a memory cell. The depression is arranged between strip-shaped isolating structures. Areas of a lower region of the depression are provided with a capacitor dielectric of a storage capacitor. A storage node of the storage capacitor is arranged in the lower region of the depression. A lower source/drain region of a vertical transistor is arranged in the substrate and is electrically connected to the storage node, with the result that the transistor and the storage capacitor are connected in series and form the memory cell. A first side wall of the depression is provided with a gate dielectric in an upper region of the depression. A gate electrode of the transistor is arranged in the upper region of the depression, said gate electrode being electrically insulated from the storage node. A word line runs above a main area of the substrate and transversely with respect to the isolating structures and adjoins the gate electrode. An insulating layer is arranged over the word line. Side walls of the word line are provided with insulating spacers. A bit line runs transversely with respect to the word line. Parts of the bit line are arranged between the spacers of mutually adjacent word lines and adjoin upper source/drain regions of the transistors of memory cells which are arranged on the main area of the substrate. The upper source/drain regions are isolated from one another by the depressions and the isolating structures and adjoin them.
The invention is based on the insight that it is advantageous to deposit materials having high electrical conductivities, such as metals for example, above the substrate since, on the one hand, they cover edges, formed for example by depressions in the substrate, poorly, that is to say non-uniformly, and, on the other hand, they should be arranged at a distance from the substrate in order to avoid contamination of the substrate. Moreover, mechanical strain or damagexe2x80x94caused by the depositionxe2x80x94of a surface of the substrate are thereby avoided.
Furthermore, the invention is based on the insight that the materials having high electrical conductivities are preferably applied at the end of a fabrication method, to ensure that there are no subsequent process steps at high temperatures which lead to degradation of underlying layers through interdiffusion in interfaces between the layers and the materials.
Since both the bit lines and the word lines run above the substrate they can contain materials having high electrical conductivities. Furthermore, the bit lines and/or the word lines can be produced at the same time as gate electrodes or transistors of a periphery of the DRAM cell arrangement by a layer or a layer sequence made of conductive materials being patterned by etching with the aid of a mask. The bit lines and the word lines have a so-called planar construction. In contrast to this, word lines and bit lines of the DRAM cell arrangement from the patent specification 195 19 160 cited above, which are arranged in depressions or are parts of the substrate, can have only a, rather, low electrical conductivity, the consequence of which is that electrical connections to higher, lower-impedance wiring planes already have to be produced after a small number of memory cells, with the result that the packing density of the DRAM cell arrangement is decreased and the complexity is increased through the number of wiring planes.
Both the word lines and the bit lines are produced after the production of the memory cells, so that metals can be used without the risk of contamination of the substrate or some other interaction with the substrate.
The bit lines can be produced by depositing and patterning one or more conductive materials with the aid of a strip-shaped photoresist mask whose strips run parallel to the isolating structures and at least partially do not cover the upper source/drain regions. As an alternative, an insulation covers the word lines, so that when the upper source/drain regions are uncovered, second trenches are produced in the insulation. The bit lines can be produced in a self-aligned manner, i.e. without the use of a mask to be aligned, in the second trenches by the conductive materials being deposited and etched back and/or subjected to chemical mechanical polishing until the insulation is uncovered.
Since the transistors are arranged as vertical transistors above the storage capacitors, the DRAM cell arrangement can have a high packing density. The space requirement per memory cell may amount to 4F2. To that end, the first trenches are produced with the aid of a photoresist mask whose strips have widths and distances between one another which amount to F. The strips of the photoresistor mask for the production of the depressions likewise have a width of approximately F and have distances between one another which amount to F. It lies within the scope of the invention if the aforementioned widths and distances amount to more than F.
The isolating structures enable self-aligned production of the upper source/drain regions between depressions that are adjacent to one another in the direction of the course of the bit lines. The upper source/drain region can be produced by patterning a doped layer of the substrate which adjoins the main area. The patterning is effected by the production of the isolating structures and of the depressions. As an alternative, the upper source/drain region can be produced by producing the depressions and the isolating structures and then carrying out an implantation.
It lies within the scope of the invention if, after the production of the depressions, the capacitor dielectric is applied and the depressions are then filled with conductive material up to a middle height. To that end, conductive material, such as doped polysilicon for example, can be deposited, planarized and etched back down to the middle height. Afterward, uncovered parts of the capacitor dielectric are removed, with the result that the capacitor dielectric covers areas of the depressions up to the middle height. Afterward, the depressions are filled further with conductive material up to an upper height, which lies above the middle height. The conductive material forms the storage nodes which adjoin the substrate between the middle height and the upper height. The lower source/drain regions are produced in such a way that they adjoin the storage nodes between the middle height and the upper height.
The lower source/drain regions can be produced from a doped layer buried in the substrate. The patterning is effected by the production of the isolating structures and of the depressions. As an alternative, the lower source/drain regions can be produced by dopant diffusing from the storage nodes into the substrate as a result of a heat-treatment step. This alternative is advantageous because channel regions of the transistors which are arranged between the isolating structures and the depressions and between the upper source/drain regions and the lower source/drain regions can be electrically connected to one another, with the result that floating body effects are avoided.
It is advantageous if the lower source/drain regions of the transistors in each case adjoin only the first side wall of the respectively associated depression and, in particular, not a second side wallxe2x80x94opposite to the first side wallxe2x80x94of the depression. Accordingly, the capacitor dielectric has a single cutout between the middle height and the upper height, which is situated on the first side wall of the depression and at which the storage node adjoins the lower source/drain region. This configuration makes it possible to increase the packing density of the DRAM cell arrangement since a distance between the second side wall and the first side wall of mutually adjacent depressions can be reduced without producing leakage currents between the associated storage nodes.
In order to produce such a DRAM cell arrangement, after the filling of the depressions up to the middle height, a photoresist mask is applied which covers the second side walls of the depressions. The uncovered parts of the capacitor dielectric are removed selectively with respect to the photoresist mask, with the result that the capacitor dielectric is preserved on the second side walls of the depressions. After the removal of the photoresist mask, the depressions, as already described, are filled further with conductive material up to the upper height, with the result that the storage nodes adjoin the substrate only at the first side walls of the depressions between the middle height and the upper height.
It is advantageous if the lower source/drain region which adjoins the first side wall of the associated depression does not adjoin the second side wall of a depression adjacent to the depression. This prevents driving of the associated transistor by the gate electrode of the adjacent depression.
The capacitor dielectric may also have a cutout on the second side wall of the depression. To that end, the photoresist mask which covers the second side walls of the depressions is dispensed with. The lower source/drain region comprises two parts. A first part of the lower source/drain region adjoins the first side wall and a second part of the lower source/drain region adjoins the second side wall of the depression. If the isolating structures are situated higher than the middle height, the capacitor dielectric also has cutouts on the remaining side walls of the depressions. The lower source/drain region is configured correspondingly.
Lower source/drain regions that are adjacent to one another transversely with respect to the isolating structures are preferably isolated from one another by the isolating structures. In this case, the lower source/drain region is arranged higher than a lower edge of the isolating structures, e.g. in the upper region of the depression. Consequently, a part of the storage node is also arranged in the upper region, and the middle height lies in the upper region. The first side walls of the depressions run transversely with respect to the course of the isolating structures.
In order to prevent a gate electrode of a depression from driving a transistor of the adjacent depression, it is advantageous if insulating structures which are thicker than the gate dielectric are arranged on the second sidewalls of the depressions. In order to increase the packing density, it is advantageous here if the insulating structures are arranged in the upper regions of the depressions instead of in the substrate. In order to produce the insulating structures, the word lines are produced offset with respect to the depressions in such a way that the gate electrodes adjoin parts of the first side walls which are provided with the gate dielectric, but not the second side walls of the depressions. During the production of the word lines, a strip-shaped photoresist mask is used whose strips cover the first side walls of the depressions but not the second side walls. Afterward, insulating material is deposited and etched back, with the result that the insulating structures are produced in a manner adjoining the second side walls.
A capacitor electrode of the capacitor is arranged in the substrate and adjoins the capacitor dielectric. The capacitor electrode may be configured as a doped substrate layer common to all of the capacitors. The doped layer may be produced e.g. by epitaxy or implantation prior to the production of the memory cells. As an alternative, a dopant source is introduced in the depressions, from which source dopant diffuses into the substrate, and forms the doped layer there, in a heat-treatment step.
The dopant source is e.g. arsenic glass. After the production of the depressions, the arsenic glass is deposited, with the result that areas of the depressions are covered. The lower regions of the depressions provided with the arsenic glass are filled with e.g. photoresist. Uncovered arsenic glass is subsequently removed. It is advantageous to grow a protective oxide after the removal of the photoresist. The protective oxide prevents arsenic from evaporating during the subsequent heat-treatment step during which arsenic diffuses from the arsenic glass into the substrate. The capacitor electrode is produced as an arsenic-doped part of the substrate which surrounds the lower regions of the depressions.
It is advantageous if the first sidewall is plane in the upper region of the depression and is curved in the lower region of the depression. The growth of the gate dielectric produced by thermal oxidation depends on the orientation of the relevant parts of the first sidewall relative to the crystal structure of the substrate. If these parts of the first sidewall are plane, the gate dielectric can grow homogeneously since a plane area, in contrast to a curved area, has a defined orientation relative to the crystal structure. Control characteristics of the transistor in which the gate dielectric has a homogeneous thickness have a particularly high subthreshold transconductance. If a part of the capacitor dielectric is grown by thermal oxidation on an area having an edge, the oxide turns out to be particularly thin on the edge. It is therefore possible for leakage currents to arise in the region of the edge. Therefore, it is advantageous if the capacitor dielectric is produced on an area having no edges. Even if the capacitor dielectric is produced by depositing material, edges in the area have a disadvantageous effect since field distortions occur at the edges and can reduce the breakdown voltage of the capacitor.
It lies with in the scope of the invention if the upper region has an essentially rectangular cross section which is larger than a cross section of the lower region, which is essentially circular or elliptic. To that end, after the production of the upper regions of the depressions, auxiliary spacers are produced in the depressions by depositing material and anisotropically etching it back. The auxiliary spacers are rounded by an isotropic etching process, with the result that uncovered parts of bottoms of the depressions have a circumference without corners. The lower regions of the depressions are subsequently produced by anisotropic etching selectively with respect to the auxiliary spacers.
In order to increase the capacitance of the storage capacitor, it is advantageous if the lower region of the depression is subsequently extended by isotropically etching the substrate, with the result that its cross section is enlarged. This enlarges the area of the lower region on which the capacitor dielectric is arranged, with the result that the capacitance of the storage capacitor is increased.
It is advantageous if the capacitor dielectric has a first part, which covers areas of the lower regions of the depressions up to a lower height, which lies below the middle height, and a second part, which is thicker than the first part and covers areas of the depressions between the lower height and the middle height.
Depending on the conductivity types chosen, a pnp junction or an npn junction is formed by the lower source/drain region, the substrate and the capacitor electrode, which junction, driven by the storage node, can cause leakage currents. Thus, if the capacitor dielectric is particularly thick between the capacitor electrode and the second source/drain region, the storage node no longer drives the junction and leakage currents are avoided.
In order to produce such a capacitor dielectric, after the production of the depression, the first part of the capacitor dielectric is applied over the whole area. Afterward, the depressions are filled with conductive material up to the lower height and uncovered parts of the first part of the capacitor dielectric are removed. Afterward, the second part of the capacitor dielectric is applied over the whole area and removed by being etched back on horizontal areas. The depressions are subsequently filled with conductive material up to the middle height, as already described.
A method is described below which prevents the situation where, on account of the finite selectivity of etching processes, an upper area of the isolating structures lies below the main area after the production of the depressions. Prior to the production of the isolating structures, a lower layer made of a first material is applied on the main area and an upper layer made of a second material is applied over said lower layer. The isolating structures are subsequently produced, the first material being used to fill the first trenches. An upper area of the isolating structures lies above the main area but below an upper area of the lower layer. By depositing and planarizing the second material until the lower layer is uncovered, auxiliary structures made of the second material are produced above the isolating structures. Afterward, the depressions are produced with the aid of the strip-shaped mask by firstly etching the first material selectively with respect to the second material, with the result that the upper area of the isolating structures lies above the main area in an unchanged manner, since the auxiliary structures protect the isolating structures. The depressions can subsequently be produced by etching uncovered parts of the substrate, the isolating structures and the lower layer serving as mask. In this case, on account of the finite selectivity of the etching process, the isolating structures and the lower layer are removed whose upper areas do not sink below the main area on account of the sufficient thickness of the lower layer during the production of the depressions.
The substrate may contain silicon and/or germanium and is preferably monocrystalline in order that the gate dielectric can be produced by thermal oxidation.
The bit lines and the word lines may be constructed in a multilayer manner. By way of example, it is possible to provide in each case a lower layer made of doped polysilicon and, above that, a layer made of a material having better electrical conductivity, e.g. silicide or metal.